Sea Forth Architecture

The IntellaSys SEAforth architecture consists of a collection of microcontroller groups on a single chip. Each group consists of four C18 cores. The earliest chip, the SEAforth-24, contained four groups, while the latest chip, called 40C18, contains ten. Each core, in turn, maintains 64 18-bit words of RAM, and a similar amount of ROM. A single 18-bit word may contain up to four C18 instructions, allowing adequate room for most tasks.

Each processor communicates with its neighbor via I/O ports which implement the semantics for CommunicatingSequentialProcesses in hardware. Therefore, despite the relative, even abject, simplicity of the MachineForth language used to program the cores, writing and exploiting fully parallel applications becomes routine.

For an example of a moderately complex program for the chip, refer to the source code found here: http://www.falvotech.com/content/publications/software-defined-video/s24-video-clock.tar.gz . The source file clock.vf contains the top-most level of code.
CategoryForth CategoryConcurrency

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